1 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com WED8L24514V may 2000 rev. 1 eco #12800 fig. 1 pin names block diagram pin symbols pin configuration asynchronous sram, 3.3v, 512kx24 features 512kx24 bit cmos static random access memory array ? fast access times: 10, 12, and 15ns ? master output enable and write control ? three chip enables for byte control ? ttl compatible inputs and outputs ? fully static, no clocks surface mount package ? 119 lead bga (jedec mo-163), no. 391 ? small footprint, 14mmx22mm ? multiple ground pins for maximum noise immunity single +3.3v ( 5%) supply operation dsp memory solution ? motorola dsp5630x ? analog devices sharc tm description the WED8L24514Vxxbc is a 3.3v, twelve megabit sram con- structed with three 512kx8 die mounted on a multi-layer laminate substrate. with 10 to 15ns access times, x24 width and a 3.3v operating voltage, the WED8L24514V is ideal for creating a single chip memory solution for the motorola dsp5630x or a two chip solution for the analog devices sharc tm dsp. the single or dual chip memory solutions offer improved system performance by reducing the length of board traces and the number of board connections compared to using multiple monolithic devices. the jedec standard 119 lead bga provides a 61% space savings over using three 512kx8, 400 mil wide sojs and the bga package has a maximum height of 110 mils compared to 148 mils for the soj packages. 12 3 45 67 anc ao a1 a2 a3 a4 nc bnca5a6e0a7a8nc c i/012 nc e2 nc e3 nc i/00 d i/013 vcc gnd gnd gnd vcc i/01 e i/014 gnd vcc gnd vcc gnd i/02 f i/015 vcc gnd gnd gnd vcc i/03 g i/016 gnd vcc gnd vcc gnd i/04 h i/017 vcc gnd gnd gnd vcc i/05 j n c gnd vcc gnd vcc gnd n c k i/018 vcc gnd gnd gnd vcc i/06 l i/019 gnd vcc gnd vcc gnd i/07 m i/020 vcc gnd gnd gnd vcc i/08 n i/021 gnd vcc gnd vcc gnd i/09 p i/022 vcc gnd gnd gnd vcc i/010 r i/023 a18 nc nc nc a17 i/011 t n c a9 a10 w a11 a12 n c u n c a13 a14 g a15 a16 n c a 0-18 address inputs e chip enable w master write enable g master output enable dq 0-23 common data input/output vcc power (3.3v 5%) gnd ground nc no connection 512k x 24 memory array 19 a 0 -a 18 g w e 0 e 2 e 3 dq 0 - 7 dq 8-15 dq 16-23
2 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com WED8L24514V may 2000 rev. 1 *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. note: for t ehqz , t ghqz and t wlqz see figure 3. absolute maximum ratings ac test conditions recommended dc operating conditions fig. 2 fig. 3 (f=1.0mhz, vin=vcc or vss) these parameters are sampled, not 100% tested. dc electrical characteristics truth table capacitance 353 ? 5 pf d out 319 ? vcc r l = 50 ? v l = 1.5v q z0 = 50 ? z 0 = 50 ? 65 pf parameter sym conditions min max units 10ns 12-15ns operating power supply current icc1 w= vil, ii/o = 0ma, 450 350 ma min cycle standby (ttl) supply current icc2 e > vih, vin < vil or 150 150 ma vin > vih, f= mhz full standby cmos icc3 e > vcc-0.2v 90 90 ma supply current vin > vcc-0.2v or vin < 0.2v input leakage current ili vin = 0v to vcc 10 10 a output leakage current ilo v i/o = 0v to vcc 10 10 a output high volltage voh ioh = -4.0ma 2.4 v output low voltage vol iol = 4.0ma 0.4 0.4 v parameter sym min typ max units supply voltage vcc 3.135 3.3 3.465 v supply voltage vss 0 0 0 v input high voltage vih 2.2 -- vcc+0.3 v input low voltage vil -0.3 -- 0.8 v voltage on any pin relative to vss -0.5v to 4.6v operating temperature ta (ambient) commercial 0 c to + 70 c industrial -40 c to +85 c storage temperature -55 c to +125 c power dissipation 1.5 watts output current. 50 ma input pulse levels vss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load figure 2 parameter sym max unit address lines ca 8 pf data lines cd/q 10 pf write & output enable lines w, g 8 pf chip enable lines e , e2, e3 8 pf ge 0 e 2 e 3 w mode output power x h h h x standby high z icc2,icc3 h l l l h output deselect high z icc1 l l l l h read (24 bit) d out icc1 l l h h h read dq 0-7 icc1 l h l h h read dq 8-15 icc1 l h h l h read dq 16-23 icc1 xllll write (24 bit) d in icc1 x l h h l write dq 0-7 icc1 x h l h l write dq 8-15 icc1 x h h l l write dq 16-23 icc1
3 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com WED8L24514V may 2000 rev. 1 ac characteristics read cycle fig. 4 read cycle 1 - w high, g, e low fig. 5 read cycle 2 - w high a q t avqv t elqv t glqv t elqx t glqx t avav t ehqz t ghqz g e a q t avqx t avqv t avav data 2 address 1 address 2 data 1 note 1: parameter is guaranteed, but not tested. symbol 10ns 12ns 15ns parameter jedec alt. min max min max min max units read cycle time t avav t rc 10 12 15 ns address access time t avqv t aa 10 12 15 ns chip enable access time t elqv t acs 10 12 15 ns chip enable to output in low z (1) t elqx t clz 33 3ns chip disable to output in high z (1) t ehqz t chz 567ns output hold from address change t avqx t oh 33 3ns output enable to output valid t glqv t oe 567ns output enable to output in low z (1) t glqx t olz 00 0ns output disable to output in high z(1) t ghqz t ohz 567ns
4 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com WED8L24514V may 2000 rev. 1 note 1: parameter is guaranteed, but not tested. ac characteristics write cycle fig. 6 write cycle 1 - w controlled a d t avwh t elwh t whax t wlwh t dvwh t wlqz t whqx t avwl t whdx t avav data valid high z w e q symbol 10ns 12ns 15ns parameter jedec alt. min max min max min max units write cycle time t avav t wc 10 12 15 ns chip enable to end of write t elwh t cw 899ns t eleh t cw 899ns address setup time t avwl t as 000ns t avel t as 000ns address valid to end of write t avwh t aw 8910ns t aveh t aw 8910ns write pulse width t wlwh t wp 81011ns t wleh t wp 81011ns write recovery time t whax t wr 000ns t ehax t wr 000ns data hold time t whdx t dh 000ns t ehdx t dh 000ns write to output in high z (1) t wlqz t whz 05 06 07ns data to write time t dvwh t dw 567ns t dveh t dw 567ns output active from end of write (1) t whqx t wlz 333ns
5 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com WED8L24514V may 2000 rev. 1 fig. 7 write cycle 2 - e controlled commercial (0 c to +70 c) industrial (-40 c to +85 c) ordering information package no. 391 119 lead bga jedec mo-163 a d t aveh t eleh t ehax t dveh t ehdx t avav data valid high z w t wleh e q t avel 0.110 max 0.711 (0.028) max 1.27 (0.050) typ 1.27 (0.050) typ a b c d e f g h j k l m n p r t u 14.00 (0.551) typ a1 corner 20.32 (0.800) typ 22.00 (0.866) typ 7.62 (0.300) typ r 1.52 (0.062) max (4x) all linear dimensions are in millimeters and parenthetically in inches part number speed package (ns) no. WED8L24514V10bc 10 391 WED8L24514V12bc 12 391 WED8L24514V15bc 15 391 part number speed package (ns) no. WED8L24514V12bi 12 391 WED8L24514V15bi 15 391
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